[SOLVED] problem with file read mode

read_values: process
             file fp: TEXT open READ_MODE is "Addizione.txt";
             variable ln: line;
             variable x, y: std_logic_vector (31 downto 0);
             variable i: integer := 0;
             begin    
                 while endfile( fp ) /= true loop --fai modifica Menichelli
                     readline( fp, ln );read( ln, x );read( ln, y );
                     test_vector_1(i) <= x;
                     test_vector_2(i) <= y;
                     i := i+1;
										 end loop;
                 test_vector_length <= i;
             wait;
     end process read_values;

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    use IEEE.std_logic_textio.ALL;
    use std.textio.all; -- utilizzo del file txt

entity testbench_adder_32bit is
    generic (T0: time:= 500 ns;
             period: time:= 5000 ns);
    port (
       A, B: out std_logic_vector(31 downto 0) := conv_std_logic_vector(0,32); -- li setto a 0
       Cin: out std_logic := '0';
       S: in std_logic_vector(31 downto 0) := conv_std_logic_vector(0,32);
       S_ref: in std_logic_vector(31 downto 0) := conv_std_logic_vector(0,32);
       Cout: in std_logic := '0';
       Cout_ref: in std_logic := '0'
    );
end testbench_adder_32bit;


architecture testbench_carry_select_adder_32bit of testbench_adder_32bit is
    type test_vector_type is array (0 to 9999) of std_logic_vector (31 downto 0); -- modifica il numero da 9 a 9999 !!!!!!!!!!!!!!!!!!!!!!!!!!
    signal j: integer := 0; 
    signal reference_clock: std_logic := '0';
    signal T0_clock: std_logic := '0';
    signal T0_Cout: std_logic := '0';
    signal T0_reg: std_logic_vector (31 downto 0) := conv_std_logic_vector(0,32);
    signal test_vector_1: test_vector_type;
    signal test_vector_2: test_vector_type;
    signal test_vector_length: integer := 0;
    begin 
        reference_clock <= not reference_clock after period/2.0;
        T0_clock <= transport reference_clock after T0;
        
        
    read_values: process
             file fp: TEXT open READ_MODE is "Addizione.txt";
             variable ln: line;
             variable x, y: std_logic_vector (31 downto 0);
             variable i: integer := 0;
             begin    
								 FILE_OPEN(fp, "Addizione.txt" );
                 while not endfile( fp )  loop --fai modifica Menichelli
                     readline( fp, ln );read( ln, x );read( ln, y );
                     test_vector_1(i) <= x;
                     test_vector_2(i) <= y;
                     i := i+1;
										 end loop;
                 test_vector_length <= i;
             wait;
     end process read_values;
     
     
     input_generator: process (reference_clock)
        begin
            if reference_clock'event and reference_clock = '1' then
                if j < test_vector_length then
                     A <= (test_vector_1(j));
                     B <= (test_vector_2(j));
                     j <= j+1;
                elsif j = test_vector_length then
                    j <= j+1;
                end if;
            end if;
        end process input_generator;
        
        
        --output_check: process (reference_clock)
               --begin
                   --if reference_clock'event and reference_clock='1' then
                      -- ASSERT (S = S_ref )or (Cout = Cout_ref) REPORT "Attenzione uscite diverse!" SEVERITY FAILURE;
                   --end if;
        --end process output_check;
        
        
        output_at_T0: process (T0_clock)
        begin
            if T0_clock'event and T0_clock = '1' then
                T0_reg <= S;
                T0_Cout <= Cout;
            end if;
        end process output_at_T0;
        
        
        write_result: process( reference_clock )
        file fpo: text open write_mode is "C:\Users\Ing. Corini Manuel\Desktop\Tesina ASI2\test_results_32bit.txt";
        variable lno: line;
        variable xo: bit_vector(32 downto 0);
        variable yo: bit_vector(31 downto 0);
        begin

            if reference_clock'event and reference_clock = '1' then
                if j/=0 and j<=test_vector_length then
                    yo := to_bitvector( test_vector_1(j-1) );
                    write( lno, yo );
                    write( lno, ht );
                    yo := to_bitvector( test_vector_2(j-1) );
                    write( lno, yo );
                    write( lno, ht );
                    xo := to_bitvector( T0_Cout&T0_reg );
                    write( lno, xo );
                    write( lno, ht );
                    xo := to_bitvector( Cout&S );
                    write( lno, xo );
                    writeline( fpo, lno );
                end if;
            end if;
        end process write_result;

end testbench_carry_select_adder_32bit;