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Difference between using multipliers and multiplied widths for transistors in Cadence

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harpv

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I'm designing a constant-gm bias circuit using Cadence IC514 and I have a doubt regarding the use of multipliers for transistor M20(in figure). I tried simulating by keeping
1) (W/L)20 = 4(W/L)21 (no. of multipliers = 4) and
2) (W/L)20 = (4*W/L)21 (no. of multipliers = 1)

While simulating across the 4 (ff,ss,fs,sf) corners case 1) shows big variations in current(almost 20µA), but not so much in case 2)(only 5-6µA difference). Does anyone know why?

I'm using 0.5µ AMIS technology for the design.

bias_circuit.png
 

When you multiply W simply, you defeat 3/4 of the
deltaW the models may be varying for corners cases.
You should be consistent in how you define W; I prefer
to always use the drawn layout actual dimension and
presume this is the foundry modeling folks' basis.

w for actual drawn width, m for actual number of drawn
fingers.

A delta-W variation modeling error could help or hurt
you, when it comes down to cases. "Two wrongs make
a right" style. According to SPICE. But at least proper
geometry modeling eliminates false mismatch terms from
the picture, leaving you with primary values to work on.
 

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