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NMOS AND2 and NAND2 Circuit? How?

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2wice

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Can someone explain to me or show me a circuit where AND and NAND can be made using only with nMOS rather than with pMOS and nMOS. I think if one of those is inverted then we could get the other and NMOS inverter is easy.
 

Thanks a lot. Can you explain to me what the VGG is for? Is VGG = VDD?
 

VGG sets the logc 1, i.e. 1=Vgg-Vth. Ideally should be larger that VDD, but VDD works too.
 

VGG sets the logc 1, i.e. 1=Vgg-Vth. Ideally should be larger that VDD, but VDD works too.
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The paper discusses different types of transistor loads, using both enhancement (Vt>0) and depletion mode (Vt<0) transistors. In practice, it depends on available transistor technology. I think that the circuits at page 10 ("Static AND, OR & XOR Gates") are realistic examples.
 

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