asicdesigner2014
Newbie level 2
I'm trying to map a design generated low frequency clock of khz range to clock port of ILA core in chipscope PRo (.cdc) file. When I program and run the bitstream in fpga, it flags the message "Waiting for Core to be armed, slow or stopped clock".
When I tie the clock port to on board system clock or DCM clock, it's fine.
Kindly advise how to hook up generated clock.
Thanks
When I tie the clock port to on board system clock or DCM clock, it's fine.
Kindly advise how to hook up generated clock.
Thanks