Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] How to determine the limit of group delay distortion for BPSK in IF filters

Status
Not open for further replies.
O

OmerN

Newbie level 4
Joined
Dec 21, 2011
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,306
Hi all. I have a question about how to determine the limit of group delay distortion for binary psk when IF filter is used. I dont know how I can decide the value. Please help..

Thanks
 

Because group delay affects BER it depends by the BER target, and also depends by the type of the filter used, by filter order, and by filter bandwidth.
The best answer can be given by a system simulation, which includes above inputs.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top