skal81
Full Member level 2
Hi all,
I'm starting a transconductor design using 0.13u CMOS, and I'd like to estimate the distortion, so I started to simulated the transistors. I apply a constant Vds, of 0.05V and I vary the Vgs to plot Ids, the gm, gm' and gm''.
I assumed I~gm*Vgs+1/6*gm''Vgs^3, and tried to check with distortion simulation. I used the QPSS analisys to find the IIP3. In that case the slope of 1st order harmonic corresponds to gm, but the 3rd order slope is quite different from 3/4*1/6*gm''.
I'm wondering:
- why is there a difference? I've seen similar idea in the ISSCC 2003 paper "A 2GHz 16dBm IIP3 Low Noise Amplifier in 0.25μm CMOS Technology" by Y-S. Youn (paper 25.7).
- does anyone have another method to propose?
Thanks for your help and comments
I'm starting a transconductor design using 0.13u CMOS, and I'd like to estimate the distortion, so I started to simulated the transistors. I apply a constant Vds, of 0.05V and I vary the Vgs to plot Ids, the gm, gm' and gm''.
I assumed I~gm*Vgs+1/6*gm''Vgs^3, and tried to check with distortion simulation. I used the QPSS analisys to find the IIP3. In that case the slope of 1st order harmonic corresponds to gm, but the 3rd order slope is quite different from 3/4*1/6*gm''.
I'm wondering:
- why is there a difference? I've seen similar idea in the ISSCC 2003 paper "A 2GHz 16dBm IIP3 Low Noise Amplifier in 0.25μm CMOS Technology" by Y-S. Youn (paper 25.7).
- does anyone have another method to propose?
Thanks for your help and comments
