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Case statement inside if-else in verilog

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sun_ray

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Can a case statement be written inside the if-else statement in Verilog? For example, can the case statement be inside the else part of an if-else statement?

Regards,

sun_ray
 

But if I have an if else statement for a sequential circuit like. flip flop or any other sequential circuit. Can we nest case statement inside that i--else statment by writing a case statement inside the else portion?

Regards
 

In terms of the Verilog LRM, a conditional or case statement can be used in place of a simple statement (See A.6.4 Statements) This already answers your question.
 

FVM

I do not have the LRM now open in front of me. Can you please let me know what this simple statement mean?
Can you also please answer my question directly?

Regads
 

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