Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Hold violation on clock gating path

Status
Not open for further replies.
R

ramesh28

Member level 3
Joined
May 21, 2013
Messages
57
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,670
Hello all,

How hold violation is taken care of if it is on clock gating path?
Which are the reasons because of hold violation occurs on clock gating path?

Can we fix it manually by adding buffers?

Reply,

Thank you..
 

The clock gating hold violation is usually because: the clk_gate_enb reach the gating cell too fast than the clock signal.
So, of cause you can add buffer on the clk_gate_enb path to eliminate the hold violation.
(Assume the clk_gate_enb and clock signal are SYNC to each other)
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top