electrobuz
Member level 2
I want to send a byte from one fpga and catch it on another. I am using parallel communication for it. In the code below, I want first value being sent to be stored in D1 and the next in D2.
I am getting the following warning:
"WARNING
hysDesignRules:372 - Gated clock. Clock net NState_or0000 is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop."
Code:
architecture Behavioral of main1 is
signal D1,D2,D3: std_logic_vector(6 downto 0);
signal PState,NState: integer:=0;
signal flag: std_logic:='0';
begin
process(I,PState)
begin
case PState is
when 0 =>
if I(0) = '1' then
NState <= 1;
else
NState <= 0;
end if;
when 1 =>
D1(6 downto 0) <= I(7 downto 1);
flag <= '1';
NState <= 2;
when 2 =>
if flag = '1' then
D2(6 downto 0) <= I(7 downto 1);
end if;
--NState <= 0;
when others=>NULL;
end case;
LED <= D1;
end process;
process(CLK)
begin
if CLK'event and CLK = '1' then
PState <= NState;
end if;
end process;I am getting the following warning:
"WARNING
hysDesignRules:372 - Gated clock. Clock net NState_or0000 is sourced bya combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop."
