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[SOLVED] Synchronizing FIFO using handshaking protocols and dual port SRAM (64x4)

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luttie

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Hi all!

can u help me to make a verilog code on designing synchronizing FIFO for data transfer from CLK0 to CLK1 using handshaking protocols and dual port SRAM (64x4)?

CLK 0 = 50 MHz
CLK 1 = 15 Mhz

with the following inputs and outputs:

Read Process:
input rd_clk;
input rd_rst;
input rd_en;
output [3:0] rd_dat;
output fifo_empty;

Write Process:
input wr_clk;
input wr_rst;
input wr_en;
input [3:0] wr_dat;
output fifo_full;


you can extend your help by sending email to me at fullakevin@yahoo.com

thank you very much! :)
 
Last edited:

luttie said:
Hi all!

can u help me to make a verilog code on designing synchronizing FIFO for data transfer from CLK0 to CLK1 using handshaking protocols and dual port SRAM (64x4)?

CLK 0 = 50 MHz
CLK 1 = 15 Mhz

with the following inputs and outputs:

Read Process:
input rd_clk;
input rd_rst;
input rd_en;
output [3:0] rd_dat;
output fifo_empty;

Write Process:
input wr_clk;
input wr_rst;
input wr_en;
input [3:0] wr_dat;
output fifo_full;


you can extend your help by sending email to me at fullakevin@yahoo.com

thank you very much! :)
Click to expand...



hi Luttie..
m not the expert one, but i remember IP core generation tool allow you to define a FIFO with different input/output data width and different i/o synchronizing clocks too...
you should read about the FIFO generation, download this document (UG175 FIFO GEN V8.4) and i hope you ll find some good luck.
 


Sir i need verilog not vhdl.. by the way tnx for the reply. :)
 

So if you need it in Verilog...translate the VHDL to Verilog. Or study the VHDL design and write your own Verilog equivalent. The code has comments so read them.

You'll learn more by doing than having the answer given to you.

Regards
 

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