Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Error in verilog A design

Status
Not open for further replies.
S

srini.pes

Member level 3
Joined
May 28, 2010
Messages
61
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Location
NIT calicut
Activity points
1,725
Hi to all,

I am designing one model in verilogA. My equation is like

Qs_low1 = Charge_low(`alpha_1,H1,b1_1,b0_1)-Charge_low(`alpha_1,L1,b1_1,b0_1);




All H1,b1_1,bo_1,L1 are declared as real.

It was showing the error at "," after H1, if i replace H1 with some integer then the error was showing at next ",".

What may be the error please clarify.

Thanks
 

Here is the function charge_low,
and alpha_1 is a constant.


analog function charge_low;
input x,y,b1,bo;
real x,y,b1,bo;
begin
charge_low = eeta(x,y)*((b1*(y-(1/2*x)))+(2*b0))+((b1)/(4*hsppow(x,1.5)))* hspln(((0.5+(x*y))/(hspsqrt(x)))+(eeta(x,y)));
end
endfunction

 

What simulator do you use ?

Try few simulators, such as HSPICE, XA, Spectre, eldo, ADSsim, GoldenGate, etc....
As far as my experience, I often encounter bug in HSPICE Verilog-A compiler.
 

Solved

error was font change in function declaration and using in program.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top