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[SOLVED] VHDL and Verilog difference

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Mina Magdy

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could any one told me what is the different between (Variable in VHDL and reg in Verilog ) and (Signal in VHDL and wire in Verilog)
 

The things you mention are not comparable. You might as well ask whats the difference between an integer in C and the letter 'E'

Variables in VHDL similar to blocking assignments in verilog
Signals are like non-blocking in verilog
 
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