vrarjun
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Hello,
I am simulating a 16 bit MIPS netlist in Icarus Verilog.
This is the error i get in testbench
mips_16_core_top_tb_0.v:144: error: Scope index expression is not constant: i
mips_16_core_top_tb_0.v:144: error: Unable to bind wire/reg/memory `uut.register_file_inst.reg_array' in `mips_16_core_top_tb_0_v.display_all_regs'
Related code :
task display_all_regs;
begin
$display("display_all_regs:");
$display("------------------------------");
$display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7");
for(i=0; i<8; i=i+1)
$write("%d\t",uut.register_file_inst.reg_array); <--- error points to this line
$display("\n------------------------------");
end
endtask
I do get this same error when i sumlate the RTL too but i still get the vcd file dumped out.In case of the netlist,I dont even get the vcd file generated.
Would be glad to hear your thoughts.
regardsm
Arjun
I am simulating a 16 bit MIPS netlist in Icarus Verilog.
This is the error i get in testbench
mips_16_core_top_tb_0.v:144: error: Scope index expression is not constant: i
mips_16_core_top_tb_0.v:144: error: Unable to bind wire/reg/memory `uut.register_file_inst.reg_array' in `mips_16_core_top_tb_0_v.display_all_regs'
Related code :
task display_all_regs;
begin
$display("display_all_regs:");
$display("------------------------------");
$display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7");
for(i=0; i<8; i=i+1)
$write("%d\t",uut.register_file_inst.reg_array); <--- error points to this line
$display("\n------------------------------");
end
endtask
I do get this same error when i sumlate the RTL too but i still get the vcd file dumped out.In case of the netlist,I dont even get the vcd file generated.
Would be glad to hear your thoughts.
regardsm
Arjun
