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LDO at no load condition

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Shrouk Shafie

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Hi all ,
Am designing a cap-less LDO/

While simulating at no load, stability of the circuit went totally loose. Although it is stable at any other load. Does anyone have an idea how to deal with this ?
Should I use a certain compensation scheme for the OTA, although it has enough phase margin ?!

Thanks in advance.
 

You might instead assert a minimum load, or set values for
the feedback divider network that impose a minimum load
current. Or make the output stage more like Class AB, with
a "braking" NMOSFET. Any of these will limit how high the
output impedance, and how low-frequency the output pole
can be.
 

The regulator, did it start to oscillate or only lost regulation?
 

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