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CMRR change with ICMR

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Dear all

I have an old problem, I posted before but i didnt get an exact answer, therefore I am re-putting with a picture to make it more clear.

I am simulating the CMRR with the input common mode range (ICMR). at the higher ICMR I am getting less CMRR. may be one would say of course because the current source is changing, but I put an ideal current source and the input transistors current are identical. in addition I am using a current mirror Op-amp so both have the same identical load .

According to [Jakob book, P.722-723], at higher voltage I should get higher CMRR if I am using an actual current source, but I am always getting the same problem.

see the picture please


I would appreciate your kind help
 

Hello,

Just wondering but you are sweeping your ICMR to 5V, is this your supply? Lets say you have a diff pair with NMOS inputs and PMOS active load single ended. What is the supply on your PMOS? Is it around 1.2V? Additionally, even thou your current mirror is ideal, don't forget your body effect of your input transistors will change, therefore the Vths will increase... maybe this is the reason...

Lastly, you make the statement, you have a current mirror Op-amp so they both have the same identical load. This is only true if its diff in diff out with a common mode feedback.

Hope this helps,

JGK
 
Hello Jg2004

first thank you

you have mentioned the change of the threshold voltage with respect to input common mode range (ICMR) as a result of the bulk effect, However I have shorted the bulk to the source in the simulated results so this effect is no more valid,

Any way, for my self I believe completely that the offset voltage changes with the ICMR and I simualted it, so obviously the CMRR has to reduce. The only thing I can not understand is, why Baker is saying that at the higher input ICMR ,the CMRR will be better.

jgk2004 said:
Hello,

Just wondering but you are sweeping your ICMR to 5V, is this your supply? Lets say you have a diff pair with NMOS inputs and PMOS active load single ended. What is the supply on your PMOS? Is it around 1.2V? Additionally, even thou your current mirror is ideal, don't forget your body effect of your input transistors will change, therefore the Vths will increase... maybe this is the reason...

Lastly, you make the statement, you have a current mirror Op-amp so they both have the same identical load. This is only true if its diff in diff out with a common mode feedback.

Hope this helps,

JGK
Click to expand...
 

VCM(in) changes the headroom on the diff pair and its loads.
Take either end out of saturation and the FET Ro drops,
taking gain with it. CMRR is largely determined by the amplifier
gain.
 

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