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Testing counter for testibility

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sarah1

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Hi,I am new here.Any body could answer the problem would be much appriciated.I dont have much time I need to do it before deadline

I have got a 16 bit up- down counter with asynchronous preset and synchronous clear.how would you design it for tetebility.
 

A counter accepts incoming pulses and sends a binary representation of the value to the output pins.

If you mean that it is one chip with 16 terminals (or two chips with 8 each)...

Then one way to test it would be to put an LED on each pin, and watch for the characteristic binary counting pattern.

Another way would be to attach seven-segment decoder chips (4 of them) to the 16 pins, and watch the hex numbers.
 

If your intention is to inspect the result through vision, Yes Proceed as "BradtheRad" said but make sure you use slow speed clock in order to make it readable with eyes. Because if the clock rate is @ Mhz, then all you gonna see is just all leds lit but no count action.
 

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