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  1. #1
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    regarding inputs to cts

    what are inputs i should get to build a clock tree...

    i have to generate specification file apart from that what are all we need

    •   Alt6th December 2012, 04:27

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  2. #2
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    Re: regarding inputs to cts

    You need target skew, clock buffer list, max trans constraint for sinks , max trans constraint for buffers & max Cap too.
    You have some target for insertion delay, then give that too, otherwise in first pass let the tool build clock tree.

    Then for better optimization you need
    custom ignore pin list, leaf pin group & through pins ..

    For achieving better skew cross corner you need maxdistance & max fanout constraint plus multi corner libs ..

    If tool can build clock tree considering derates, then you need those too ..
    Last edited by curty; 6th December 2012 at 17:50.



    •   Alt6th December 2012, 06:50

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  3. #3
    rca
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    Re: regarding inputs to cts

    EDI used the SDC file to know the clock source.
    EDI defined function of the technology node (setDesignNode), the MaxSkew, the Sink/MaxTran, the delay, the period and from the library the cell could be used.
    All of these parameters could be changed by this command: "specifyClockTree -update { AutoCTSRootPin * MaxSkew 400ps} (as example)

    - - - Updated - - -

    The problem of the technology node definition, it does not take care of std cell power supply (I means at 0v9 you don't expect the same trans as 3v3)
    and also for technology node higher than 180nm, the "default" values are not realistic.



    •   Alt6th December 2012, 08:21

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  4. #4
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    Re: regarding inputs to cts

    You can use "createClockTreeSpec" for creating clk spec file in CDN . For creating spec file it will use information from SDC to create spec file ..



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