verilogproject
Newbie level 1
I am doing a home alarm system project in system verilog. I am using a 12 bit keypad input to enter the 5 digit password. Each digit is encoded by an encoder and then finally it compare with the original stored the password.
My question is how will we input digits? Do I need to input each digit during positive edge of clock cycles? Do I need to design states in fsm while I am entering each digit?
My question is how will we input digits? Do I need to input each digit during positive edge of clock cycles? Do I need to design states in fsm while I am entering each digit?