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basic verilog questions??

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mohi@608

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A wish to design a module ...i have two methods one is writing the functionality of all sub components in same module(let the tool do all the work ) or making separate module for each sub component and calling it in the top module...
which approach is better ????

i have another doubt can we have multiple begin in a single always block ..could you please explain with an example ???
 

hi mohi

Its our wish to design the module !!!

up to me if u have separate module and u call in the main u feel easy to understand and also it s easy to find the bugs!!


ya u can have multiple begin in a single block
.
https://www.doulos.com/knowhow/verilog_designers_guide/if_statement/

this link will give u an idea about this i hope!!
---------
sujeethaa
 
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For simple designs there is no need to use multiple modules and then connect them together.
But when the design becomes more complicated, such as a processor, it is better to use this method called bottom-up mean you break the design into small
pieces, and then you connect them together.

- - - Updated - - -

For simple designs there is no need to use multiple modules and then connect them together.
But when the design becomes more complicated, such as a processor, it is better to use this method called bottom-up mean you break the design into small
pieces, and then you connect them together.
 

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