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VHDL alias synthesizability

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shaiko

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Are VHDL aliases always synthesizable ?
 

One experience I have had is that I could leave out the optional subtype indication in Modelsim but the synthesis tool required it.
 
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    shaiko

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My Doulos golden reference guid recommends not using them, but it is a few years old now. I would probably stear away from them, because I cant think of any situation where an alias is a neccessity.
 
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