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How to generate 2 clock outputs in ISE 6.3?

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voho

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how to generate clock

Hi

I use ISE6.3 and i have input clk100Mhz and i want to generate 2 outputs one 25Mhz and other 50Mhz if free IPcore in vhdl is available.

Thank's
 

how to generate clock

IP core??? All you need is two flip-flops.
 

Re: how to generate clock

Use DCM
 

Re: how to generate clock

DCM is better choice if your target contain it, What specific family do you want to use?
 

how to generate clock

Salam Johnson,

I'm a beginner too.

For example i use Spartan-3 XC3S200, it contains 4 DCMs (Digital CLock Manager)

Can you explain how to generate the clock using DCM? My main clock source is 50Mhz (attached at T9 pin)

Thanks
 

how to generate clock

DCM adds jitter and startup delay. Don't use it unless you need aligned phase. Voho didn't request that.

SphinX, try the Xilinx Libraries Guide. If you find it confusing, don't feel bad! Just tell us which HDL language you are using, your desired input/output frequencies, and maybe someone here can give you a code snippet.
**broken link removed**
 

Re: how to generate clock

If this is a hobbyist/school thing, use a simple counter/divider circuit and refrain from DCM.

Delay
 

Re: how to generate clock

Hi,

I agree, 2 FFs would do. It depends what you want to do with ur clocks, a DCM could be considered. If the fan out of your divided clocks is high then make sure u use a BUFG to use dedicated resources and reduce skew.

process(reset,clk_100m)
begin
if reset then
clk_cnt <= (others => '0');
elsif rising_edge(clk_100m) then
clk_cnt <= clk_cnt + 1;
end if;
end process;

clk_50m_i <= clk_cnt(0);
clk_20m_i <= clk_cnt(1);

i_clk50m_bufg : BUFG
port map (
I => clk_50m_i,
O => clk_50m
);

--maestor
 

Re: how to generate clock

hi all

I use xc2v3000 and i have esternal clk at 100MHz my design works at 50Mhz.

Maestro: clk_cnt it's a vector 1 downto 0

Muchas gracias
Merci
Thank's in advance
 

how to generate clock

Have a look at Spartan3 user guide, there is a chapter about how to use DCM.

Cheers,
zcq
 

how to generate clock

i don't think using 2 filp-flop is a good idea. it may cause uncertain delay and skew. a best idea is to use DCM or DLL ,and you should and bufg too.
 

Re: how to generate clock

voho,

it is funny you are getting too many answers but no one is prviding with the following:

1) VHDL Design of the Module
2) TestBench of the Module

let me know if you still haven't solved the problem yet.

Good Luck
 

Re: how to generate clock

I believe that it only depends upon the application, i.e. if you need some fixed or variable phase difference in your design, a DCM is a good choice and the jitter can be accepted at 100 MHz, however if the phase is not an issue in your design you can use the two FFs idea but take care that the output of the last FF should be tied to a BUFG also the FF itself should be near a BUFG this will decrease the jitter and the skew problem, actually if you have enough resources on your FPGA don't go to the plan B stick with the DCM "more reliable'

that's all folks
 

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