Ultra high speed data acquisition system ???

I want to make a data acquisition system of which the bandwidth is about
1.5GHz, can anybody give me some advices on how to realize it,
thanks in advance!!

Gregcooler said:

I want to make a data acquisition system of which the bandwidth is about
1.5GHz, can anybody give me some advices on how to realize it,
thanks in advance!!

Click to expand...

Hello Gregcooler,

Could you give a more precise description of what you want to build?
It is one thing to make a system that is capable of measuring repetitive
1.5GHz signals. It's quite another to build something that's capable of
single shot @ 1.5GHz. Well, let's keep it simple and assume that 1.5GHz
single shot is right out in a hobby setting.

1.5GHz repetitive. Main ingredients for such a system are the analog
frontend (with 1.5GHz bandwidth), and a sampler. The sampler can sample at a
much lower frequency, say for example 200 MSPS. This technique is called
equivalent-time sampling, and is used in DSOs. For a description, see:
https://www.tek.com/Measurement/App_Notes/RTvET/ap-RTvET.html

This way you can achieve high repetitive bandwidth with reasonably low-cost
ADCs. A nice part to start experimenting with this sort of thing is the
the adc08200 from natsemi, $15 @ digikey.
https://www.digikey.com/scripts/us/dksus.dll?Detail?Ref=17942&Row=124673

Analog bandwidth of the input is 500 MHz, so not exactly what you want, but
you can start experimenting for a nice price. A few more things you have to
take into account is:
Make sure you have a low jitter clock source, and make sure the aperture of
your sample and hold stage is as small as possible. If the S&H of your ADC
of choice is not good enough you can slap on a seperate IC to do the job.
Analog Devices makes some nice ones, but Analog is usually a bit expensive.

An easy way to start playing is take an fpga evaluation board, connect your
favorite ADC to the fpga board, and of you go. Of course you have to keep in
mind that the clock jitter on a cheapo fpga board is not all that great, but
hey, it's a cheap experiment.

Few random links on this subject:
**broken link removed**
**broken link removed**
https://www.xilinx.com/apps/sp2eapp.htm
**broken link removed**
https://www-users.york.ac.uk/~jke1/#RF
I have more of the same and a few appnotes if you are interested.

Executive summary: Proposed plan is feasible, but prototyping with a lower
bandwidth version might be advisible.