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cver simulator instantiation problem

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maheshkumar.g

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hi all,
i am new to this forum, i have a doubt on verilog simulation, i am doing 4 bit ripple carry adder program where i intantiated full adder and i am able to execute the ripple carry adder program only if the fulladder program is with in the folder where my riplle carry adder program is present. And when i call it from another folder it says unresolved UDPS please let me know whether i can call the full adder from another folder.

my verilog program:

Code Verilog - [expand]
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module fa4(s,c,a,b,ci);
input [3:0] a,b;
output [3:0] s,c;
input ci;
fa f0(s[0],c[0],a[0],b[0],ci);
fa f1(s[1],c[1],a[1],b[1],c[0]);
fa f2(s[2],c[2],a[2],b[2],c[1]);
fa f3(s[3],c[3],a[3],b[3],c[2]);
endmodule

hope u people reply me as soon as possible
 
Last edited by a moderator:

put fa module in the same file fa4 module is
 

tariq786 said:
put fa module in the same file fa4 module is
Click to expand...

thanks,but i want to know whether we can call the modules from different directory or not instead of copying them on to the program and also can we create global modules so that we can call them if so please explain it with an example....thanks in advacnce
:???:
 

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