micro designer
Junior Member level 2
problem in verilog-A model of second order sigma delta modulator pls help!!!
iam working on the verilog-A modeling of first and second order DT sigma delta modulator in synopsys custom designer.
verilog-A code for filter is shown below :
module filter(vin,vout);
input vin;
output vout;
electrical vin, vout;
parameter real n0 = 1.0;
parameter real T = 7.8125e-7 from (0:inf);
parameter real t = 2n from (0:inf);
parameter real d0 = 1.0;
parameter real d1 = -1.0;
analog begin
V(vout) <+ zi_nd (V(vin) , {n0} ,{d0, d1},T );
end
schematic is here
first order sdm is working properly as shown in the figure
but when the second order sdm is simulated the output is negative Vmax ie 0.8 V in this case. The filter outputs are going in one direction only as shown here View attachment filter1_out.pdfView attachment filter2_out.pdf instead of
in case of first order sdm.
Can anybody help me to understand this problem. Is it required to add saturation blocks after the filter to limit their outputs ?
Thank you
iam working on the verilog-A modeling of first and second order DT sigma delta modulator in synopsys custom designer.
verilog-A code for filter is shown below :
module filter(vin,vout);
input vin;
output vout;
electrical vin, vout;
parameter real n0 = 1.0;
parameter real T = 7.8125e-7 from (0:inf);
parameter real t = 2n from (0:inf);
parameter real d0 = 1.0;
parameter real d1 = -1.0;
analog begin
V(vout) <+ zi_nd (V(vin) , {n0} ,{d0, d1},T );
end
schematic is here
first order sdm is working properly as shown in the figure
but when the second order sdm is simulated the output is negative Vmax ie 0.8 V in this case. The filter outputs are going in one direction only as shown here View attachment filter1_out.pdfView attachment filter2_out.pdf instead of
in case of first order sdm.Can anybody help me to understand this problem. Is it required to add saturation blocks after the filter to limit their outputs ?
Thank you
