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how display states in vhdl testbench

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lahrach

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Hi friends;

How can I display states of FSM in my vhdl testbench

example:

type type_test_state is ( IDLE,
STATE_TEST,
SEND_FINISH
);

signal current_s, next_s : type_test_state;

regards
 

By which you mean that would like to see the enumerated type, as opposed to the binary value? If so, good question! I'd like to know this as well for either modelsim or isim. A bit of a workaround is if your states are one-hot, then you can label each of the bits with the corresponding state. But as said, that's a bit of a workaround. It would be neater to use the enum.

Oh yeah, even if it's not one-hot, you could use a function to go from binary to one-hot and then use that with the aforementioned workaround.

Update: check out http://www.da.isy.liu.se/~ehliar/stuff/ and **broken link removed** for a modelsim tcl script.
 
Last edited:

Hi mrflibble,

yes I have one hot machine
can you give an example of testbench

thanks
 

type type_test_state is ( IDLE,
STATE_TEST,
SEND_FINISH
);

virtual type {IDLE STATE_TEST SEND_FINISH} mystatetype
virtual function { (mystatetype)Give hierarchy name of signal which you wantto convert} myconvertedsignal
add wave myconvertedsignal
 
If you are doing RTL testing, the states should just show as they are. I assume you're talking about a post place and route testbench?
 

TrickyDicky,

They will be shown as binary values. Not the names.
 
TrickyDicky,

They will be shown as binary values. Not the names.

No they wont, because in an RTL test they have not been assigned binary values yet - this is done by the synthesisor and different settings are used to assign them. You can control the assignments yourself in the synthesisor settings, but the default for altera is a count sequence for 3 or less states, or one hot for more (IIRC). You can change this yourself either via the settings or via attributes, and you can select count, 1-hot ot grey code.

So given that the OP wanted to know how to see the states, I assumed he could only see a binary value - which means he is doing a post synthesis simulation.
 

Yes I am talking about the scenario when the vhdl is written for synthesized RTL.
 
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