lahrach
Full Member level 3
Hi friends;
How can I display states of FSM in my vhdl testbench
example:
type type_test_state is ( IDLE,
STATE_TEST,
SEND_FINISH
);
signal current_s, next_s : type_test_state;
regards
How can I display states of FSM in my vhdl testbench
example:
type type_test_state is ( IDLE,
STATE_TEST,
SEND_FINISH
);
signal current_s, next_s : type_test_state;
regards