[SOLVED] SDC, Virtual Clock, IO Constraints, early vs. min

Hi,

I'm new to this forum and at first I want to say "Congratulations" to your work. Great community where I often found help in the past. But now, I've got a questions and so I hope you can help me.

I'am doing my first chip and in approx. 1 week it is tape-out deadline and I'm nearly finished. But now I want to recheck my constraints while synthesis and pnr. At this moment I only constraint my IOs with set_input_delay regarding to the master clock. Now I want to use a virtual clock for better IO constraints how described here: **broken link removed**

If I understand this example correct, the virtual clock in the circuit in front of the chip arrives 1 ns later then the master clock and the clock pin of the ASIC. This is exactly what I need. In my case the Circuit in front of the ASIC is an FPGA, so I can shift the clock. Therefore I want to say: "the delay of the clock in the FPGA is at least 1 ns and at most 3 ns". So there is not only one valid case and the FPGA design is easier. But how to tell this in sdc (for design compiler, encounter, prime time)?

I found set_clock_latency -source -min and -max
and set_clock_latency -source -early and -late

So what is the difference between? And what should I use for my case? For example:
set_clock_latency -source -max 3 or set_clock_latency -source -late 3

Thank you very much for your help,

Marc

There are two forms of clock latency: source and network. Source latency is the propagation delay from the origin of the clock to the clock definition point (for example, a clock port), and network latency is the propagation delay from a clock definition point to a register’s clock pin. The total latency (or clock propagation delay) at a register’s clock pin is the sum of the source and network latencies in the clock path.

You can use the set_clock_latency command to specify input delay constraints to ports in the design. The following list shows the set_clock_latency command including the available options:

set_clock_latency
-source
[-rise | -fall]
[-late | -early]
<delay>
<object list>
Table 1 describes the options for the set_clock_latency command.

Table 1. Options Description for set_clock_latency Command
Option Description
-source Specify a source latency.
-rise | -fall Specify the rising or falling delays.
-late | -early Specifies the earliest or the latest arrival times to the clock.
<delay> Specifies the delay value.
<object list> Specifies the clocks or clock sources if a clock is clocked by more than one clock.

Hallo,

thank you for your answer. Now, I'am able to constraint my IOs exactly.

Greetings,

Marc