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Help me ( CMOS INVERTER )

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angbong

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I'm designing a CMOS inverter circuit.
Right side graph is output voltage.
My question is why is there a peaking at 1us, 2us, ...(yellow mark)
and how can i remove it?
캡처.PNG
 

It is caused by the gate-drain capacitance of the MOSFETs, which directly couple the input signal to the output. If you slow the rise time of the input signal, the spike should get smaller or disappear.
 
Spikes caused by Cgd of real MOSFET.

how can i remove it?
Click to expand...
- use input signal with realistic rise- and fall time
- add some load capacitance
 

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