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integer in verilog synthesize to

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rknmahesh

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Generally if I declare a variable as integer in verilog.. What hardware element the synthesis tool will take that variable.


Thanks in advance
 

As far as I'm aware of, integer will be used only for variables that don't infer hardware register, e.g. an iteration loop variable. In some cases, an integer variable will be assigned to a signed or unsigned vector, but it doesn't infer hardware elements on it's own. If you know cases that are sugesting hardware use, please tell.
 

If not initialized in a iteration loop or even in a iteration loop it should remember its own previous value which infers as a memory. So I think it may be inferred as register only may be... As I also dont know some one help...
 

An iteration loop isn't actually "executed" at runtime. It's just a method to describe parallel logic. In so far loop variables aren't hardware objects.
 
Ya I too agree but what if its not a iteration loop lets say a counter incrementing evry posedge of clock
 

In case of doubt, presume a 32 bit register. You're possibly able to constrain it to a specific bit width in the assignment. Check the result with your synthesis tool.
Code: 
 if (i < 7)
   begin
     i<= (i + 1) & 7;
     q <= 0;
   end
 else
   begin
     i<=0;
     q <= 1;
   end;
 

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