victor.tomov
Newbie level 4
Hi all,
I have a simple question about the case statement in Verilog. Is there anyway to write something similar to this VHDL code:
where N is parameter.
What I need is to map the cases in Verilog let say from N-1 to 0 to one logic expression.
Thanks in advance.
VT
I have a simple question about the case statement in Verilog. Is there anyway to write something similar to this VHDL code:
Code:
case state_reg is
when (N-1) downto (0) =>
....
What I need is to map the cases in Verilog let say from N-1 to 0 to one logic expression.
Thanks in advance.
VT