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Verilog FSM Case Statement

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victor.tomov

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Hi all,

I have a simple question about the case statement in Verilog. Is there anyway to write something similar to this VHDL code:
Code:
case state_reg is
when (N-1) downto (0) =>
....
where N is parameter.

What I need is to map the cases in Verilog let say from N-1 to 0 to one logic expression.

Thanks in advance.
VT
 

Verilog also has a case statement. Here is an example of how to implement a 4:1 multiplexer using a case statement in Verilog...

Code:
module multiplexor4_1 (out, in1, in2, in3, in4, cntrl1, cntrl2);
           output out;
           input  in1, in2, in3, in4, cntrl1, cntrl2;
           reg      out;

           always @(in1 or in2 or in3 or in4 or cntrl1 or cntrl2)
              case ({cntrl1, cntrl2})
             2'b00 : out = in1;
             2'b01 : out = in2;
             2'b10 : out = in3;
             2'b11 : out = in4;
             default : $display("Please check control bits");
              endcase
        endmodule

Regards,
Willis
 

module multiplexor4_1 (out, cntrl1, cntrl2, in);
output out;
input in, cntrl1, cntrl2;
reg out;

always @(in or cntrl1 or cntrl2)
case ({cntrl1, cntrl2})
2'b00 || 2'b01 || 2'b10 || 2'b11 : out = in;
default : $display("Please check control bits");
endcase
endmodule

Hope it works
 
Last edited:

Hey, thanks for the replies.
Maybe I didn't express myself very good in the previous post. What I want to know is there a way to write parametric statement in the case logic? For example:
Code:
parameter N = 8;

always @(in1 or in2 or stage_reg)
              case (stage_reg)
             {from N to 0} : out = in1;
             {from N+1 to N+4} = in2;
             default : $display("Please check control bits");
              endcase
where {from ... to...} should be proper Verilog case item.

Thanks,
VT
 

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