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Large holding cap leads to higher current rating in a rectifier?

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iVenky

iVenky

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I was reading a paper on implementing rectifier in CMOS technology. I read that a large holding capacitor is needed (at the output) in order to get a high current rating. How do you say that?

Thanks a lot. :)
 

δV/δt = I/C . Larger C enables lower voltage drop. Additionnally, larger C has lower ESR.
 

If you relate the question to power rectifiers, larger cap means higher peak current and thus higher Irms/Iavg ratio, in other words lower current rating.
 

FvM said:
If you relate the question to power rectifiers, larger cap means higher peak current and thus higher Irms/Iavg ratio, in other words lower current rating.
Click to expand...

Okay. Basically I need a large capacitor in the IC that I design. But I don't it to consume the space in my IC. I thought of using Miller Technique to boost the capacitance using an amplifier and a small capacitor but most of the papers suggest that there is a problem in it. Can you tell me what that problem exactly is?
 

Miller capacitance is obviously not related to power rectifiers. But I don't know which problem you are referring to.
 

iVenky said:
Okay. Basically I need a large capacitor in the IC that I design. But I don't it to consume the space in my IC. I thought of using Miller Technique to boost the capacitance using an amplifier and a small capacitor but most of the papers suggest that there is a problem in it. Can you tell me what that problem exactly is?
Click to expand...

A capacitance multiplier can be a way to obtain a greater value. Don't know for sure if it suits your design.

https://en.wikipedia.org/wiki/Capacitance_multiplier
 

iVenky said:
... most of the papers suggest that there is a problem in it. Can you tell me what that problem exactly is?
Click to expand...

The method works only dynamically, but you can't multiply a static capacitance. In other words: you can use the multiplication effect e.g. to filter AC voltages, but you can't multiply the capacitance to store a larger DC energy.
 

erikl said:
The method works only dynamically, but you can't multiply a static capacitance. In other words: you can use the multiplication effect e.g. to filter AC voltages, but you can't multiply the capacitance to store a larger DC energy.
Click to expand...

Even in large signal the capacitance gets multiplied (for eg: we see in digital VLSI circuits about this in CMOS inverters parasitic capacitance). But I haven't seen any papers regarding this basically (i.e. boosting the o/p capacitance through miller technique). Basically I need a large capacitor at the output of the recitifier IC which I am building. As I have told you before the problem is that I can't make a huge capacitor using MOS. So my Professor asked me if I could use a Miller capacitance to multiply the capacitance. But he told me that there is a problem in it and many papers discuss about that issue. But I searched the ieee xplore but I couldn't get anything. If you see any paper regarding just cite me the paper title.

Thanks a lot
 

If we are using an inverting amplifier of gain -A as a miller capacitance multiplier for a real capacitor value C, we get a multiplied virtual capacitor of (A+1)*C at the amplifier input. If Vdd is the maximum amplifier output swing, the maximum virtual capacitor voltage will be Vdd/A. Either if you consider the reduced value as "large" or "small" signal, the reduced voltage swing is probably the most serious problem if you consider a large signal application.
 

Additionnally, larger C has lower ESR.
Click to expand...
Hi Dear Erikl
I'm not sure about it ! because i had this problem in many of my designs , when capacity , is larger , ESR is larger too . perhaps your mean was another thing ?
Best Regards
Goldsmith
 

erikl said:
Additionnally, larger C has lower ESR.
Click to expand...

goldsmith said:
... i had this problem in many of my designs , when capacity , is larger , ESR is larger too . perhaps your mean was another thing ?
Click to expand...

No. Larger C goes along with larger area which means less resistance (due to paralleling). See the Ta cap tables below. Larger caps (in the same package) tend to have lower ESRs.
 

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FvM said:
If you relate the question to power rectifiers, larger cap means higher peak current and thus higher Irms/Iavg ratio, in other words lower current rating.
Click to expand...



iVenky said:
I was reading a paper on implementing rectifier in CMOS technology. I read that a large holding capacitor is needed (at the output) in order to get a high current rating. How do you say that?
Click to expand...


I am confuse when I read these two statements.
Can anyone explain me whether these two statements are correct or either of them are a wrong statement?
or is it not a valid que. to ask to relate these both statements?
 

Hi dear Erikle , again .
For example a 100 nf capacitor . and a 4700 uf capacitor . i have used them in a transmitter with surge current of 10 A at frequency of 3 MHZ . that electrolytic capacitor became very hot and when i have replaced it with that ceramic capacitor , the problem solved . ( it was a test ) what can be the reason in your idea ?
( I agree a tantalum capacitor has very low ESR , but how about electrolytic capacitors ? ( for more capacity more rolling is required . ( longer distance ) hence their ESR will be increased . )
Best Regards
Goldsmith

- - - Updated - - -

By the way i saw datasheet of some of capacitors , you are right they wrote lower ESR too . ( as your file shows too ) Now i think that warming was because of ESL . am i right ?
Thank you
Goldsmith
 

Can anyone explain me whether these two statements are correct or either of them are a wrong statement?
Click to expand...
The question can't be answered without clarifying the capacitor purpose.
 
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