sheikh
Advanced Member level 4
Hello Dear experts
I have an ASM an I extracted a Data Path from it. This Data Path contains 7 ADD/SUB and 8 Multipliers units and when I see it on paper, it seems a little big. I don't have any experience in real implementation of a design in to a FPGA, So please tell me according to your experience, if I use this amount of ADD/SUB and multipliers, does it consume a lot of sources of a FPGA (spartan3, for instance) ? Is it necessary to use hardware replication technique, for instance, to reducing the amount of hardware, or not?
Regard
Mostafa
I have an ASM an I extracted a Data Path from it. This Data Path contains 7 ADD/SUB and 8 Multipliers units and when I see it on paper, it seems a little big. I don't have any experience in real implementation of a design in to a FPGA, So please tell me according to your experience, if I use this amount of ADD/SUB and multipliers, does it consume a lot of sources of a FPGA (spartan3, for instance) ? Is it necessary to use hardware replication technique, for instance, to reducing the amount of hardware, or not?
Regard
Mostafa