Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

DFT ; ATPG : with no sdf simulation

Status
Not open for further replies.

rahul_neil1

Newbie level 2
Joined
Aug 21, 2012
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,294
Hi, I am simulating the pattern generated by tetramax in ncverilog. I have used no timing check off. This is just a basic scan chain shift test. My chain is failing right from the start ...with the below message :

Netlist : {dc generated}

>> Error during scan pattern 1 (detected from unload of pattern 0)
>>> At T=637315.00 ns, V=6374, exp=0, got=1, chain chain13, pin out1, scan cell 0

What can be the cause.. I am seeing that the SI is also 1...its very difficult to trace back ..

Can it happen becoz of zero simulation ....

Option used :
+nclicq +delay_mode_unit +nospecify +notiming_check +access+rwc +nctimescale+1ns/10ps +noassert +define+ATPG+DUMP
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top