using use ieee.std_logic_signed.all; and numeric ??

which better when usign (+) addition in a code

you cannot do unsigned+ with std_logic_signed.
they are different.

std_logic_signed works on std_logic_vectors. It is NOT part of the VHDL standard. You cannot do unsigned arithmatic in the same file.
numeric_std works on signed and unsigned types. It is part of the VHDL standard. It makes for clearer code and you can do signed and unsigned in the same file.

So numeric_std always. Forget about using std_logic_signed ever again.

You can just import numeric_std and std_logic_signed. Or better, just import "+" and "-" from std_logic_signed. (ieee.std_logic_signed."+")

std_logic_signed might not be part of the original VHDL standard, but it doesn't mean you can't use it. It is supported by xilinx, altera, mg, synopsys, etc... You have to really try to find a commercial tool that doesn't support it.

by just picking a few functions from the std_logic_arith/signed/unsigned you can end up with something that works with numeric_std and without having to re-write your own extensions to VHDL.

The only real issue is that std_logic_signed also allows "*", "<", and ">", which are different than the unsigned versions. Verilog users would expect these to treat everything as unsigned unless specified. By importing only "+" and "-" you end up with code that allows you to add/sub using std_logic_vectors in the common cases. For anything else, you would need to specify signed/unsigned. And the meaning shouldn't be unclear to anyone reading the code.