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Basic info about reset recovery and removal time

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sun_ray

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Is reset recovery time with respect to assertion of the reset and reset removal time is with respect to reset removal time? Is there any good document which says basics about reset recovery and removal time?
 

Re: about reset in design

You can read synopsys solvnet
 

Re: about reset in design

dftrtl

Where in Solvnet it has been discussed about this kind of reset related issue?

Regards
 


Re: about reset in design

Please go through it again.
 

Re: about reset in design

dftrtl said:
Please go through it again.
Click to expand...

Went through again. At the first passage after the Answer heading it writes what I wrote before.
 

When design coming out of reset is important. We never checking when design going into RESET.
 

dftrtl said:
When design coming out of reset is important. We never checking when design going into RESET.
Click to expand...

But why is it the defined with respect to the closing/negative edge of clock?
 

It is defined with rising edge of the clock only.
 

dftrtl said:
It is defined with rising edge of the clock only.
Click to expand...

But in the above mentioned document, it is defined with respect to closing edge of clock. Closing edge means negative edge. Is not it?
 

dftrtl said:
No it is rising edge only.
Click to expand...

But the document in solvnet writes closing edge. How can a closing edge be rising edge? Closing edge should be falling edge for a positive logic digital system.
 

Some reset synchronizer circuits are registering an external reset on the falling clock edge...

 

FvM said:
Some reset synchronizer circuits are registering an external reset on the falling clock edge...

Click to expand...

FvM

What is your suggestion for this solvnet definition?
 

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