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Negative clock skew threat

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Jaffry

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Dear all,

How can I know that the negative skew I am having is in any way threat for my design.
Please see the following report. Actually I am confused how to look into this skew thing from FPGA design point of view.
I have the idea of clock skew, positive and negative but dont know its implementation in FPGA design, since the internal registers etc.
are not in my control since the software manages them all ( I am using Xilinx ISE).

I have seen some positve while other negative clock skews in my design, and one 0.00ns clock skew...Which is correct and to what extent...

Timing constraint: TS_clk_ab_p = PERIOD TIMEGRP "clk_ab_p" 200 MHz HIGH 50%;

7150 paths analyzed, 4568 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 4.595ns.
--------------------------------------------------------------------------------

Paths for end point sip_fmc104_0/fmc10x_inst/fmc10x_ctrl_inst/fmc10x_io_buf_adc_inst/fmc10x_io_buf_data_ab/cha_sdr_val (SLICE_X61Y186.DX), 1 path
--------------------------------------------------------------------------------
Slack (setup path): 0.244ns (requirement - (data path - clock path skew + uncertainty))
Source: sip_fmc104_0/fmc10x_inst/fmc10x_ctrl_inst/fmc10x_io_buf_adc_inst/ch_wren (FF)
Destination: sip_fmc104_0/fmc10x_inst/fmc10x_ctrl_inst/fmc10x_io_buf_adc_inst/fmc10x_io_buf_data_ab/cha_sdr_val (FF)
Requirement: 2.500ns
Data Path Delay: 2.098ns (Levels of Logic = 0)
Clock Path Skew: -0.123ns (1.515 - 1.638)
Source Clock: sip_fmc104_0/fmc10x_inst/clk_ab falling at 2.500ns
Destination Clock: sip_fmc104_0/fmc10x_inst/clk_ab rising at 5.000ns
Clock Uncertainty: 0.035ns
Click to expand...

I am not sure if this will help my design or not.

Bests,
Jaffry
 
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This looks like a half cycle path, since the source flop operates in falling edge (2.5 ns) and destination flop operates in rising edge (5 ns).
I am not an expert in STA. Just giving you a thought.
 

Hey, mr_vasanth raises a good point. This bit probably indicates a posedge clocked vs negedge clocked issue.

Source Clock: sip_fmc104_0/fmc10x_inst/clk_ab falling at 2.500ns
Destination Clock: sip_fmc104_0/fmc10x_inst/clk_ab rising at 5.000ns
Click to expand...


As for "which skew is correct, the positive or the negative bits?". Well, they're all correct. Some locations on the fpga die have a bit of positive skew relative to the used clock net and other locations have negative skew.
 
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