Sample-and-hold with leakage correction

I am playing with sample+hold circuits in pspice and after getting frustrated with leakage currents across mosfet hold switch I went to falstad and tried to come up with a way to compensate for the leakage using ideal and identical components. Here is part of an sh circuit (hold switch + capacitor + attempt at correction):

Falstad simulator link: https://tinyurl.com/cstu8w6



On the left, the bottom mosfet is the switch and the top is identical with 0 gate voltage. The op amp tries to eliminate current through capacitor by adjusting the mosfets on the right to allow a compensating current to pass. "Ia" is the current flowing through the 0 gate mosfet, "Ib" is the compensation current and ideally it equals Ia when the hold switch is off.

To play with it adjust the "signal" slider on the right and hold down the "sample" switch (which I should have labelled "hold") for a little while to take a sample. Bottom left scope shows capacitor voltage and current, center is Ia, right is Ib.

It reduces the leakage (note I'm also assuming an ideal capacitor and only compensating for mosfet leakage) by a factor of 10 to 100 depending on the signal and hold voltages, but as you can see Ia is not equal to Ib and so there is still leakage (the magnitude of Ia-Ib also differs depending on the state).

Why is this happening? Am I missing some fundamental thing here? I don't quite understand what is going on that is causing the currents to be different despite all of the mosfet and resistor models being identical.

Thanks!

I assume that the circuit on the right side is intended to work as a kind of active current mirror. To understand the non-ideal behaviour, you would want to look at individual branch currents and node voltages.

You didn't mention what causes the rather high leakage currents in your MOSFETs. Thus I can't determine, if a compensation should work.

Thanks!

FvM said:

I assume that the circuit on the right side is intended to work as a kind of active current mirror. To understand the non-ideal behaviour, you would want to look at individual branch currents and node voltages.

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Yes. I tried a few different methods and ended up with the mosfet circuit on the right - my first attempt use two differential amplifiers and a lot more components, the difficulty I ran into with the initial "passive" current mirror approach was finding a common source for current for the top and bottom portions. Is this a reasonable approach?

You didn't mention what causes the rather high leakage currents in your MOSFETs. Thus I can't determine, if a compensation should work.

Click to expand...

The leakage currents are caused by non-zero off resistance in the MOSFETs (also present in Falstad's MOSFETs). They are on the order of nanoamps. It is a problem in the S+H circuits I was originally playing with because I am attempting to achieve hold times of 60+ seconds with a voltage drop of, say, < 0.1 mV per 600 seconds.

But mostly here I'm just trying to find out why the leakage current isn't exactly zero in the ideal simulator -- I realize that practically it will be much more difficult. Should it be zero in the above circuit (btw the op amps are not being saturated)? I know I am missing something.

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To clarify, my goal in that circuit is for the op amp to hold the point after the resistor on top at the same potential as the capacitor by providing the same amount of offset current to both the top and bottom portions of the circuit; but the harder I think about it now the more I get confused about feedback re: an equilibrium state and the - input tracking the leakage slightly as the capacitor discharges through leakage? :-?

I don't know what an ideal simulator is. An ideal MOSFET model (simplified quadratic equation, SPICE Level 1) has Id = 0 for Vgs < Vth. A more realistic MOSFET model also implements a subtreshold region.

I was able to reduce the leakage slightly by biasing the mosfets with ~2V diodes and resistors:



The n/p mosfet thresholds are +/- 1.5V and the biasing gives ~ +/- 1.5V to gates at 0V op amp output.
In my test case (signal to 12V, hold until charged, signal to 0V), it reduced the leakage from 13.3n to 12.2n.
In my other test (signal to 0V, hold until discharged, signal to 12V), it reduced the lekage from 1n to 0.2p.

But there's still a difference coming from somewhere.

In my view, a simulator that doesn't provide devices with known model parameters and doesn't allow to modify it is useless for this kind of simulations.

FvM said:

I don't know what an ideal simulator is. An ideal MOSFET model (simplified quadratic equation, SPICE Level 1) has Id = 0 for Vgs < Vth. A more realistic MOSFET model also implements a subtreshold region.

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I'm sorry, "ideal" was a poor word choice. The relevant characteristics of this simulator are:

- op amps are rail to rail
- op amps have infinite input impedance and 0 output impedance
- op amps have no drift or offset
- I am not sure what op amp slew rate is, it is not infinite.
- IIRC the open loop gain of the op amps is 100000
- resistors are ideal, they have only resistance, with 0% tolerance
- capacitors are ideal, they have only capacitance, with 0% tolerance (no leakage)
- mosfets are not "ideal" but they are all identical (wrt channel).
- voltage sources are ideal

I think that covers most of the key points.

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FvM said:

In my view, a simulator that doesn't provide devices with known model parameters and doesn't allow to modify it is useless for this kind of simulations.

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You can modify a few basic parameters:

- rail voltage for op amps
- resistance for resistors
- capacitance for capacitors
- threshold voltage for mosfets
- forward voltage @ 1A for diodes

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Listing the features helped me think about this:

jasonc2 said:

- op amps have no drift or offset
...
- IIRC the open loop gain of the op amps is 100000

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I guess these two statement contradict. The op-amp can only get the +/- inputs within .001% of each other (right?); I am having a hard time getting my head around how that .001% (e.g. 50uV @ 5V inputs) translates to leakage current offset though, I don't know if that could be the cause?

I don't doubt, that this basic level device models will serve their purpose e.g. to visualize circuit operation. For the present problem, they obviously bring up issues that e.g. a standard single MOSFET ord complementary CMOS analog switch doesn't have.

In this case I would prefer a simple behavioral switch for the simulation, instead of designing complex compensation circuits, only needed to fix a simulator problem.

FvM said:

I don't doubt, that this basic level device models will serve their purpose e.g. to visualize circuit operation. For the present problem, they obviously bring up issues that e.g. a standard single MOSFET ord complementary CMOS analog switch doesn't have.

In this case I would prefer a simple behavioral switch for the simulation, instead of designing complex compensation circuits, only needed to fix a simulator problem.

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This is not to fix a simulator problem, it is to fix a current leakage problem in the hold switch.

Here is a paper that cites the presence of the real problem in a practical application (with a CMOS switch, incidentally), as well as a possible solution (which I will try soon): **broken link removed**

**broken link removed** is a mosfet advertised as low leakage with Idss=0.1u and Igss=100n.

The ADG604 switch (for example), has 0.1n off leakage.

Even though the switch has significantly less leakage the 0.1n leakage would still result in a 0.1mV drop after ~40 seconds with a 10u cap (@ 5V). Recall my purpose is to create a sample and hold circuit that is as solid as possible for hold times on the order of minutes.

It's actually the opposite of a simulator problem, an analog switch with 1G or so off resistance would easily solve the problem in the simulator, but that doesn't help me determine how to offset real leakage currents in a real application... I'm not sure how my question was construed as solving a simulator problem that doesn't exist in reality when, AFAIK, it is actually the opposite.

As for my choice of simulators, I should not have mentioned it, as I believe it confused the conversation. I approach design by starting simple and identifying error and uncertainty as I go, it's just how my mind works, I guess from being a programmer.

With electronic circuits that I don't fully understand, I can develop them in Falstad's simulator. When they work there I know I have the fundamental design down. The visualization helps me because I am not an experienced electrical engineer. Perhaps some day I won't use that simulator any more. Next I bring it into pspice where I can work with relatively accurate models of actual components available in the real world. I then know that errors in pspice are due to more practical limitations and behaviors of the components. I take a leap of faith and hope that the simulation models are relatively functional. Once it works there, I can build it in real life. I then know that errors are likely due to practical issues such as component tolerances, wire inductance, RF noise, but in the simulation process I've hopefully ruled out any gross design errors.

My choice of simulators here, however, is only a consequence of my thought process, it is not the cause of the problem I am attempting to solve.

Perhaps I should ask a different question:

I want a sample and hold circuit that operates on 0 to +12V signals, with a < 10ms acquisition time, and < 0.1mV droop over 600 seconds (10 minutes), and < 0.1mV hold accuracy. Can you (or anybody) recommend any designs?

Thanks!

PS In both Falstad's simulator and pspice, behavioral switches have a finite off resistance. Choosing a high enough resistance (in GΩ range) could get my circuit to spec in a simulator but I do have to think ahead a little and I know of no way to build such a high resistance switch in reality except perhaps by using a mechanical relay, which may actually be appropriate here (as long as I don't run at at min 10ms acquisition period for too long I guess, or have a lot of replacements on hand).

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To clarify: The purpose of me mentioning Falstad's simulator in the original post was to highlight that a leakage compensation circuit with identical components did not work as I expected it to, and that the problem was possibly due to a fundamental design flaw (hence my question) rather than e.g. component tolerances or temperature or emi.

So, returning to my original question, what am I missing in my leakage-compensation design that is causing it to not perform as expected, given that component tolerances etc. have been eliminated as a source of error?

Do you (or anybody) have any thoughts on my hypothesis re: gain offset from the op-amp? Are there ways to compensate for this? Can anybody help me work out the math to determine how op-amp offset translates to leakage current?

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FvM said:

You didn't mention what causes the rather high leakage currents in your MOSFETs. Thus I can't determine, if a compensation should work.

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Also, following up with this, I've since described the MOSFET leakage currents, so, then, in your opinion, can compensation work?

It's very difficult (if not impossible) to build an analog sample and hold with <0.1mv acquisition and hold accuracy from a 12V signal for 10 minutes.

I would suggest you use a digital approach. Convert the signal with an A/D converter to a digital value and then output the digital value with a D/A. That can give you the accuracy you need with an infinite hold time. Of course 0.1mV out of 12V requires over 16-bit accuracy, so this solution is not trivial to implement either, but I think it's the only one that has a reasonable chance of success. ;-)

Out of curiosity why do you need such high accuracy?

crutschow said:

It's very difficult (if not impossible) to build an analog sample and hold with <0.1mv acquisition and hold accuracy from a 12V signal for 10 minutes.

I would suggest you use a digital approach. Convert the signal with an A/D converter to a digital value and then output the digital value with a D/A. That can give you the accuracy you need with an infinite hold time. Of course 0.1mV out of 12V requires over 16-bit accuracy, so this solution is not trivial to implement either, but I think it's the only one that has a reasonable chance of success. ;-)

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Thanks; that's kind of what I expected the answer to be... still is there something wrong with my original circuit as a means for general leakage cancellation?

Out of curiosity why do you need such high accuracy?

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I am trying to determine if my suggestion in this thread is actually useful and practical. I found the problem in that post interesting. I greatly overspecified the requirements here because 0.1mV over 10 minutes @ 12V is a hard problem and I was hoping it would create an interesting discussion with informative contributions (maybe better to post in EDA Theory -> Elementary Questions instead -- or somehow work in a reference to "negative feedback" :lol.

I can only guess at what the actual requirements are as the poster did not say. The original problem was roughly to hold a 2-4V sample long enough for a li-ion cell to charge or discharge 100mV, without the use of an ADC, to some unknown degree of accuracy -- the nature of the problem in that post is such that inaccuracy in my suggestion would compound over time, so I chose .1mV as 0.1% error per step (it's the battery that's being sampled in ideally 100mV steps). The hold time for charging would be more like 90 seconds (100mV @ rough 4V/hr) and during discharge, unknown, no requirements were specified.

So you say, that you are using the Falstad simulator to evaluate a compensation circuit, that is intended to work with real MOSFETs, and leakage currents smaller by 2 or 3 orders of magnitude? That hasn't been quite obvious... (The respective comments in post #3 have been added after my latest post)

I agree that leakage currents can be a problem if you want to design charge storage circuits with large time constants, e.g. S/H or integrators. But it's not so clear that the systematical part of leakage currents is large enough in relation to the random part, so that a compensation will really reduce total leakage. You need to look at actual transistor specifications to decide about it.

I've seen similar analog storage circuits in professional instruments designed in 60s or the latest in the 70s. Since that time, digital circuits as suggested by crutschow have taken their place.

The required 0.1 mV drop/600 s/1 µF translates to 0.16 pA total leakage (switch + capacitor + buffer), at least an ambitious specification.

A compensation circuit can be expected to reduce an unwanted quantity (e.g. BJT or JFET amplifier input current) by a considerable factor. My personal rule of thumb for similar compensation problems says: factor 5 is easy, factor 10 often possible, factor 20 hard to achieve. Of course it's about real circuits and measurement systems, not simulations. And the unwanted quantity must have a mostly systematical nature, which isn't clear for the MOSFET channel leakage.

In a simulation that doesn't add artificial parameter tolerances and uses identical transistor exemplars, a "perfect" compensation should be possible. To trace the problems in the Falstad simulation, you need to know exact model parameters and look at voltages and currents, as suggested. I would try with a full featured SPICE simulator, e.g. LTSpice and real transistor models.

Thanks!

FvM said:

So you say, that you are using the Falstad simulator to evaluate a compensation circuit, that is intended to work with real MOSFETs, and leakage currents smaller by 2 or 3 orders of magnitude? That hasn't been quite obvious... (The respective comments in post #3 have been added after my latest post)
...
In a simulation that doesn't add artificial parameter tolerances and uses identical transistor exemplars, a "perfect" compensation should be possible. To trace the problems in the Falstad simulation, you need to know exact model parameters and look at voltages and currents, as suggested. I would try with a full featured SPICE simulator, e.g. LTSpice and real transistor models.

Click to expand...

I had intended to communicate most of that in the first sentence of post #1:

jasonc2 said:

I am playing with sample+hold circuits in pspice and after getting frustrated with leakage currents across mosfet hold switch I went to falstad and tried to come up with a way to compensate for the leakage using ideal and identical components.

Click to expand...

But I guess communication broke down somewhere. I did not specify the requirements I was looking for in the first post.

--

In a simulation that doesn't add artificial parameter tolerances and uses identical transistor exemplars, a "perfect" compensation should be possible. To trace the problems in the Falstad simulation, you need to know exact model parameters and look at voltages and currents, as suggested. I would try with a full featured SPICE simulator, e.g. LTSpice and real transistor models.

Click to expand...

I started with pspice, then moved to Falstad because I wanted to try leakage compensation circuits, but then I found it wasn't "perfect" in Falstad and concluded that there was something wrong with my approach, so came here.

--

I've seen similar analog storage circuits in professional instruments designed in 60s or the latest in the 70s. Since that time, digital circuits as suggested by crutschow have taken their place.

The required 0.1 mV drop/600 s/1 µF translates to 0.16 pA total leakage (switch + capacitor + buffer), at least an ambitious specification.

A compensation circuit can be expected to reduce an unwanted quantity (e.g. BJT or JFET amplifier input current) by a considerable factor. My personal rule of thumb for similar compensation problems says: factor 5 is easy, factor 10 often possible, factor 20 hard to achieve. Of course it's about real circuits and measurement systems, not simulations. And the unwanted quantity must have a mostly systematical nature, which isn't clear for the MOSFET channel leakage.

Click to expand...

Hm, that's a good rule of thumb, thanks. It seems like a digital solution would be the only way (the AD5533 looks neat but it's obsoleted for some reason). My goal was to avoid digital solutions because of that other post I referred to, although I don't know why purchasing an ADC isn't an option for that poster.

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I believe my only initial question was clearly stated, and was (and still is):

Why is this happening? Am I missing some fundamental thing here? I don't quite understand what is going on that is causing the currents to be different despite all of the mosfet and resistor models being identical.

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I am still unable to answer this. :-?

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Progress! :grin:

I guess these two statement contradict. The op-amp can only get the +/- inputs within .001% of each other (right?); I am having a hard time getting my head around how that .001% (e.g. 50uV @ 5V inputs) translates to leakage current offset though, I don't know if that could be the cause?

Click to expand...

It turns out it was the op amp's low gain (100000) that was causing the difference. I tried increasing the gain by chaining two op amps together and, at least in the Falstad simulator, reduced the ~13n leakage to 0.1p:

https://tinyurl.com/che8gug



I have a new question about this but I am going to create a new post.