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Verilog - edge sensitive reset

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shaiko

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I took a long look at this very common Verilog DFF description:

Code: 
always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end  else begin
q <= data;
end
endmodule //End Of Module dff_async_reset

something appears wrong to me.
WHY is the reset edge sensitive ???
 

This is an artifact of the way current synthesis tools want to see DFF modeled as a single process. It's also difficult to model level sensitive behavior in procedural code with out getting into infinite loops. That's why you see all combinatorial or latch logic modeled as
Code: 
always @(en or data)
   if (enable) out = data;
This code executes on any edge change to the inputs. If you did not have the @(en or data) the process you get into a zero delay infinite loop. Adding a #1 delay would break the loop, but is very inefficient for simulation because it executes every time step.

Originally, the Verilog assign/deassign procedural assignment statements was used to model level sensitive behavior as in
Code: 
always @(en)
   if (enable) assign out = data;
   else deassign out;
and you could model a DFF as two separate processes
Code: 
always @ ( posedge clk) // synchronous process
        q <= data;
always @ (reset) // asynchronous process
        if (~reset)
          assign q = 0;
        else
          deassign q;

but many people confused continuous assignments with procedural continuous assignments and the mainstream synthesis tools did not support this style of coding.
 
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    FvM

    FvM

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Dave,

you say:
This is an artifact of the way current synthesis tools want to see DFF modeled as a single process
Click to expand...

Although it synthesizes to a DFF with an asynchronous reset - would you agree that this behavioral description is fundamentally wrong?
The reset doesn't behave this way at all...it's level sensitive. Not edge sensitive

Wouldn't you say that the following description is much closer to the truth:

Code: 
always @ ( posedge clk or reset) // instead of always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end  else begin
q <= data;
end
 

This is an artifact of the way current synthesis tools want to see DFF modeled as a single process.
Click to expand...
Artifact is a good word for this contradiction in terms - using the edge keyword for a level sensitive event.

But the latest with IEEE 1364.1 Standard for Verilog Register Transfer Level Synthesis, the syntax has been accepted as the preferred method to describe a DFF with one or more additional asynchronous inputs.
 
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In an event based simulation, things only happen when there is an event, which is defined as a change on a variable or a specified amount of time passing. Even though you might have modeled something as level sensitive, the simulator only executes code when the level changes.

The problem with removing the negedge qualifier on reset is that there is no check to see which event caused the process to unblock. "@reset" means wait for any change on reset. So a change on reset from 0 to 1 will cause the if statement to execute the same as a posedge clk. Adding negedge reset filters the change the simulator is looking for to only 1 to 0.

- - - Updated - - -

FvM, as far as I know, no commercial tool claims to support this IEEE 1364.1 synthesis standard.
 
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as far as I know, no commercial tool claims to support this IEEE 1364.1 synthesis standard.
Click to expand...
You probably know better about the motivation and perspective for IEEE 1364.1 In my impression, the standard is summarizing the specific constructs that have evolved in synthesizable Verilog. I don't know if there are plans to support it explicitely in the future or if the standard will be possibly superseded. In any case, I think that the standard is effectively near to the syntax supported by existing synthesis tools.
 

The problem with removing the negedge qualifier on reset is that there is no check to see which event caused the process to unblock. "@reset" means wait for any change on reset.
Click to expand...

Indeed.
But that will only hurt simulation performance...correct ?
The code without "negedge" will still synthesize to a DFF with an asynchronous reset - right ?
 

The code without "negedge" will still synthesize to a DFF with an asynchronous reset - right ?
Click to expand...
It's not accepted by the synthesis tools. E.g. Altera Quartus gives an error:

Verilog HDL Event Control error at xxx: mixed single- and double-edge expressions are not supported
 
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shaiko said:
Indeed.
But that will only hurt simulation performance...correct ?
The code without "negedge" will still synthesize to a DFF with an asynchronous reset - right ?
Click to expand...

Not correct. if you remove the negedge qualifier, not only will it not synthesize, it will not simulate correctly. A reset transitioning from 0 to 1 will behave like a posedge clk event; q <=d will execute.
 
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