[SystemVerilog] Using strings data types to force/probe desing signals (wires)

Hi everybody,

I am writing a generic verification task so i would like to parse the information of a table including signal names for a specific digital RTL block. I thought it could be a good idea to use a string data type to hold the signal names and then try to force them or probe them within my verification task. The problem is that as far as i know system verilog does not support string data types in force/probe commands. Please see the example below:

typedef struct { byte chicken_bit;
byte num_blocks;
string blk_names[];
string blk_clk[];
string blk_en_clk_check[];
string blk_clk_req[];
int clk_freq[];
} chicken_bit_s;

chicken_bit_s chicken_bit_table[];

There is a struct holding row information from the table initialized before compilation time. Also the dynamic array chicken_bit_table contains on each index the information for a specific struct variable (row). The dynamic string arrays defined inside the struct are used because each struct copy variable can have different number of strings. For example the blk_clk [] string dynamic array is initialized to the values {"tmp1_clk", "tmp2_clk"} where tmp1_clk and tmp2_clk are actual clk wires defined in the RTL. Ideally i would like to use this string array elements to force or probe this signals in the RTL. As i said before this is not allowed in system verilog. You cannot probe or force a string. I can't also define this array as dynamic wire array and then initialize it using define commands to the hierarchy path of the actual wires.

Any suggestion to solve this issue would be really valuable for me.

Thanks in advance.

This is being discussed in the **broken link removed**