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Question About Thermal Relief Design in Cadence Allegro

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ngkl99

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hi,
I have problem in the inner layer via as attached file.
Can anyone tell me how to set correctly?

thanks!
 

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  • via.zip
    268.3 KB · Views: 100

Are you using common via for both signal and power.
Any way open your via in Pad Designer and check if thermal relief is defiened for inner layers if it is so you can make it "null".
then you will have completely filled via for all copper pours.
 

when i open the modify padstack menu,
TR_80_60 type is symbol definition (select the 'text' button)

Now, in my own pcb, i created my own symbol also.
but when i open the padstack menu,
i found that my creation type is labeled as Package.

how can i change type to "symbol definition"?

and what is the difference between package an symbol definition

thanks!
 

hi ngkl,
it is not due to via property but the copper plane property. In the first picture you defined the 2nd layer as a negative plane with GND net.
In the second case 2nd layer is a normal layer (or posetive plane) . You may make the 2nd PCB as the first one by changing display properties and plane properties.
And my doubt is do you really need a thermal relief for via???
 

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