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Combining Sysgen and VHDL

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babyeric

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I have a model in Sysgen and another model in VHDL code. I need to combine both of them together as 1 entire Project. The VHDL inputs come from the Sysgen output. The eventual output is from the VHDL block. I need to clock my Sysgen at Ts, but clock my VHDL code at Ts/2. However, when I do this, I can't get any output. Can anyone advise me whether can I use 2 different clocks for Sysgen and VHDL if the VHDL input is taking the output of Sysgen??

Hope someone can clear my doubt. Thank you.

PS: I had used 2 same clocks for Sysgen and VHDL, and I can get the correct output.
 

It will work as long as the sysgen output data rate is the same as the VHDL input data rate.

babyeric said:
I have a model in Sysgen and another model in VHDL code. I need to combine both of them together as 1 entire Project. The VHDL inputs come from the Sysgen output. The eventual output is from the VHDL block. I need to clock my Sysgen at Ts, but clock my VHDL code at Ts/2. However, when I do this, I can't get any output. Can anyone advise me whether can I use 2 different clocks for Sysgen and VHDL if the VHDL input is taking the output of Sysgen??

Hope someone can clear my doubt. Thank you.

PS: I had used 2 same clocks for Sysgen and VHDL, and I can get the correct output.
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