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[SOLVED] VHDL error:port has no source

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darshkamal

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Hello all,
I've correctly synthesized blocks. Then I'm using structural description to build the complete component.
I'm sure the connections are correct and that there're no floating i/p ports, but I get the following error during synthesis:

Xst:1706 - Unit <comp5>: port <x_real<4><7>> of logic node <slice3/slice1/x_real<4><7>_inv> has no source

and it's repeated more than once.
I'm using Xlinix ISE10.1 for synthesis.

Thank you in advance
 

I've found a solution
The solution is setting keep Hierarchy to "Yes" from Process---->properties--->keep Hierarchy
 

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