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Need help in designing RAM in Spartan 6 (using VHDL)

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juansiahaan

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Hello everyone,

I'm trying to implement a simple RAM (for the SP601 evaluation kit) that will store a 12-bit data. I've seen many sample codes from XST user guide such as this one

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity RAM_src is
    PORT (CLK : in std_logic;
            en : in std_logic;
            we : in std_logic;
            addr : in std_logic_vector (5 downto 0);
            d_in : in std_logic_vector (11 downto 0);
            d_out : out std_logic_vector (11 downto 0)
            );
 
end RAM_src;
 
architecture Behavioral of RAM_src is
type ram_type is array (63 downto 0) of std_logic_vector (11 downto 0);
signal RAM : ram_type;
signal read_a : std_logic_vector (5 downto 0);
 
begin
d_out <= RAM(conv_integer(read_a));
 
    memory: process (CLK)
    begin
    if rising_edge (CLK) then
        if en = '1' then -- enable
            if we = '1' then -- write enable
                RAM(conv_integer(addr)) <= d_in;
                read_a <= addr;
            end if;
        end if;
    end if;
    end process memory;
 
end Behavioral;


From that code, is it possible that an input is stored/written in a selected/defined address so that I only have to access that address if I want to read that data?

Also, does anyone know how to test that RAM code (with testbench, maybe)?

Regards,

Juan
 

you probably want to make read_a a port, or remove it and place the d_out line in the enable if-else statement.
 

permute said:
you probably want to make read_a a port, or remove it and place the d_out line in the enable if-else statement.
Click to expand...

Hi Permute,

do you mean like this? I made a few changes though (but not many)

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity RAM_src is
    PORT (CLK : in std_logic;
            en : in std_logic; -- global enable
            we : in std_logic; -- write enable
            addr : in std_logic_vector (8 downto 0); -- adress bit vector
            d_in : in std_logic_vector (11 downto 0);
            d_out : out std_logic_vector (11 downto 0)
            );          
 
end RAM_src;
 
architecture Behavioral of RAM_src is
type ram_type is array (511 downto 0) of std_logic_vector (11 downto 0); --512 locations in RAM
signal RAM : ram_type;
 
begin
 
    memory : process (CLK)
    begin
    if rising_edge (CLK) then
        if en = '1' then
            if we = '1' then
                RAM(conv_integer(addr)) <= d_in; -- read
            end if;
                                d_out <= RAM(conv_integer(addr)); -- write
        end if;
    end if;
    end process memory;
 
end Behavioral;


so is there any way to select the address to store input only to that address?
 

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