Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Required VHDL code for shift register

Status
Not open for further replies.
K

Khurram1965

Newbie level 4
Joined
May 26, 2012
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,342
Dear Friends, I have just start the using CPLD, I need a vhdl code for a 16 bit shift register, who serially out a 16 bit pre-defined hex code like"AC52" on each rising edge of input clock. thanks
 

I guess, you mean the input clock should work as a bit clock. But there must be a frame clock as well, either generated by your design or input to it. Reconsider and supplement your specification.
 

Yes, in other words I want to transmit serially a 16 bit pre defined code bit by bit on each rising edge of clock
 

I want to transmit serially a 16 bit pre defined code bit by bit on each rising edge of clock
Click to expand...
Yes, I know. But the specification is incomplete.

Code: 
signal sr: std_logic_vector (15 downto 0);
process (clk)
if risisng_edge(clk) then
  if load = '1' then
    sr <= x"ac52";
  else 
    sr <= sr(14 downto 0) & '0';
  end if;
end if;
serial_out <= sr(15);
end process;

The above code example shows the open points in your specification.
- how to generate the load signal?
- how to inform the receiver about start of frame?
- LSB or MSB shifted out first
 

Thank you for response, "ac52" is header of frame, I want to transmit "msb" first. Now I am able to define my frame:

Frame length = 1600 bits
Frame Header = ac52 (transmit msb first)

ac52 -----------(1584 bits"0")--------------ac52 -----------(1584 bits"0")--------------ac52
 

Respected Fellow i have write following code, it is synthesis successfully, but there is some missing in code for my requirement which is;


Frame length = 1600 bits
Frame Header = ac52 (transmit msb first)

ac52 -----------(1584 bits"0")--------------ac52 -----------(1584 bits"0")--------------ac52

Please guide/help to me for achieve the task
Thanks

********************************************************************************

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity Frameout is
  Port (
    clk         : in  STD_LOGIC;  
    load        : in  STD_LOGIC;  
    Serial_out : out std_logic);    
end Frameout;
 
 
architecture Behavioral of Frameout is
 
signal sr: std_logic_vector (15 downto 0);
begin
process (clk,load)
begin
 
if (load = '1') then
    sr <= x"ac52";
  
  else if rising_edge(clk)then 
  sr <= sr(14 downto 0) & '0';
  end if;
end if;
serial_out <= sr(15);
end process;
end Behavioral;
 
Last edited by a moderator:

the total length is 1600 bits and u want 2 transmit 16bit at every rising edge of clock , n MSB shud be transmitted first....
is dat ur question?????

if yes,
den u need to define signal 
Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

signal sr: std_logic_vector (1599 downto 0);  
signal i,j :integer range 0 to 255;
 
--and assign i=1599 and j=1583.
 
-- and ur code shud be like
 
if (load = '1') then
sr <= x"ac52";
 
else if rising_edge(clk)then
sr <= sr(i downto j) & '0';
end if;
 
i=i-16;
j=j-16;
 
end if;
serial_out <= sr(15);
end process;
end Behavioral;


i hope dis does the work...
 
Last edited by a moderator:

i hope dis does the work... .
Click to expand...
I guess, you didn't try to compile. The code is violating various VHDL syntax rules (and doesn't work if the syntax would be tolerated).

Code: 
signal sr: std_logic_vector (15 downto 0);
signal cnt: integer range 0 to 1599;
process (clk)

if risisng_edge(clk) then
  if reset = '1' OR cnt >= 1599 then
    sr <= x"ac52";
    cnt = 0;
  else 
    cnt <= cnt + 1;
    sr <= sr(14 downto 0) & '0';
  end if;
end if;
serial_out <= sr(15);
end process;
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top