Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

verilog code for a frequency multiplier

Status
Not open for further replies.

joseph1991

Newbie level 4
Joined
May 12, 2012
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,315
i really need to know if is possible to multiply a clock frequency in verilog

or maybe someone can explain me how to delay a clock signal with a quarter of a period
 

Dear

It is simple. Clocking wizard can do that for you for V6 xilinx FPGAs.

Or if using Spartan series or less than virtex 6 in virtex series, DCM can do that for you (of course Xilinx FPGAs)

Use Core Generator to launch either... It will make things clearer to you....Use **broken link removed**
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top