sukyen
Newbie level 3
I have a RAM code here in VHDL where I have to convert to Verilog.
VHDL seems very complicated on its grammar and I am new to this field.
Can anyone help me with this?? Its very urgent. Thanks in advance!
VHDL seems very complicated on its grammar and I am new to this field.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; USE STD.TEXTIO.ALL; USE IEEE.std_logic_TEXTIO.ALL; ENTITY std_logic_ram IS PORT (address : IN std_logic_vector; datain : IN std_logic_vector; dataout : OUT std_logic_vector; cs, rwbar : IN std_logic; opr : IN BOOLEAN); END ENTITY std_logic_ram; ARCHITECTURE behavioral OF std_logic_ram IS TYPE mem IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) of std_logic; PROCEDURE init_mem (VARIABLE memory: OUT mem; CONSTANT datafile: STRING) IS FILE stddata : TEXT; VARIABLE l : LINE; VARIABLE data : std_logic_vector(memory'RANGE(2)); BEGIN FILE_OPEN (stddata, datafile, READ_MODE); FOR i IN memory'RANGE(1) LOOP READLINE (stddata, l); READ (l, data); FOR j IN memory'REVERSE_RANGE(2) LOOP memory (i,j) := data(j); END LOOP; END LOOP; END PROCEDURE init_mem; PROCEDURE dump_mem (VARIABLE memory: IN mem; CONSTANT datafile: STRING) IS FILE stddata : TEXT; VARIABLE stdvalue : std_logic; VARIABLE l : LINE; BEGIN FILE_OPEN (stddata, datafile, WRITE_MODE); FOR i IN memory'RANGE(1) LOOP FOR j IN memory'REVERSE_RANGE(2) LOOP stdvalue := memory (i, j); WRITE (l, stdvalue); END LOOP; WRITELINE (stddata, l); END LOOP; END PROCEDURE dump_mem; BEGIN PROCESS CONSTANT memsize : INTEGER := 2**address'LENGTH; VARIABLE memory : mem (0 TO memsize-1, datain'RANGE); BEGIN id: IF opr'EVENT THEN IF opr=TRUE THEN init_mem (memory, "memdata.dat"); ELSE dump_mem (memory, "memdump.dat"); END IF; END IF; wr: IF cs = '1' THEN IF rwbar = '0' THEN -- Writing FOR i IN dataout'RANGE LOOP memory (conv_integer (address), i) := datain (i); END LOOP; ELSE -- Reading FOR i IN datain'RANGE LOOP dataout (i) <= memory (conv_integer (address), i); END LOOP; END IF; END IF; WAIT ON cs, rwbar, address, datain, opr; END PROCESS; END ARCHITECTURE behavioral;
Can anyone help me with this?? Its very urgent. Thanks in advance!
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