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Clock & Gated Clock -> Clock & Clock Enable

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asslowashell

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Hello! I am new here, and pretty new to FPGA design in general as I am primarily a software developer -- this is my early foray into FPGA hardware (I've done plenty of uC stuff) and I apologize in advance for stupid questions.

I am attempting to capture a Gameboy's LCD panel output to USB as an exercise prior to more and more complicated panels. The LCD panel is essentially driven with two data pins for the four shades of gray and a pixel clock which is a gated clock output based on the CPU clock of the Gameboy. I also use the VSYNC and HSYNC signals but they are irrelevant for this problem.

I need to turn this pixel clock and CPU clock into a free-running FIFO clock with FIFO write enable. The FIFO clock will be just directly based on the CPU clock; however the write enable I need which is based on if the pixel clock is toggling is the tricky part. I am trying to interface the LCD panel to a Xilinx IP Core FIFO. I already have the piece on the other side that reads from this FIFO and talks to an FX2 USB chip done and tested -- Just having problems with the LCD side of it!

I would greatly appreciate a push in the right direction. I could / probably am approaching this all wrong.
 

No question is stupid!

Can't gated clock used on the FIFO directly?
Also, I wonder if there is a way you can shift the incoming clock to 90 degree? Then, I guess it can be used as a enable signal...
 

asslowashell said:
Hello! I am new here, and pretty new to FPGA design in general as I am primarily a software developer -- this is my early foray into FPGA hardware (I've done plenty of uC stuff) and I apologize in advance for stupid questions.

I am attempting to capture a Gameboy's LCD panel output to USB as an exercise prior to more and more complicated panels. The LCD panel is essentially driven with two data pins for the four shades of gray and a pixel clock which is a gated clock output based on the CPU clock of the Gameboy. I also use the VSYNC and HSYNC signals but they are irrelevant for this problem.

I need to turn this pixel clock and CPU clock into a free-running FIFO clock with FIFO write enable. The FIFO clock will be just directly based on the CPU clock; however the write enable I need which is based on if the pixel clock is toggling is the tricky part. I am trying to interface the LCD panel to a Xilinx IP Core FIFO. I already have the piece on the other side that reads from this FIFO and talks to an FX2 USB chip done and tested -- Just having problems with the LCD side of it!

I would greatly appreciate a push in the right direction. I could / probably am approaching this all wrong.
Click to expand...

Are you asking, if you can use Pixel clock as FIFO Write enable?.
Do you have wave pattern or could you capture that pixel clock and cpu clock in an MSO\DSO (Oscilloscope)?. Also, in case if you dont have it, use chipscope to capture that clocks and check out the waveforms. This is one way to find the match, in case the source characteristics are unknown.
 

I don't think it can be used directly -- the data sheet mentions the FIFO clock must be free running for proper functionality. Shifting the pixel clock 90 degrees is a good idea! Though the waveforms in the datasheet show an enable that goes high and stays high, I think toggling it might be OK as long as it's asserting enable at the time of the FIFO clock edge! I'll try doing the phase shift with a DCM but first I gotta verify the phase shift between the pixel and CPU clocks off the GB since I am not 100% sure what that is at this moment.
 

I think I know what you are trying to do, but if this reply is wrong, please let me know...

This is assuming that there is a separate read & write clock to the FIFO.

If the clock is gated at the Gameboy end (ie its active whenever there is fresh data) then just use that as the FIFO writeside clock. Drive the writeside enable to '1'.
Then, when fresh data is available it will be delivered to the writeside in bursts that last as long as the clock is running.

You can then just read out the data from the readside and Bob's your dad's uncle....

Unless I've miss understood what the problem was?
 

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