Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

help with differential signal termination

Status
Not open for further replies.
K

kcinimod

Member level 3
Joined
Dec 19, 2011
Messages
63
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,714
hi all, i have a question on differential signal for both input and output. If i only use one of the signal (i.e. the positive signal) what should i do to the negative signal ? how should it be terminated ?
 

what's the purpose of Vtt (termination voltage) at the output pins ?
 

Sounds like you are referring to a particular IO standard, e.g. differential SSTL. It's a voltage referenced standard that requires connection of termination resistors to a reference voltage. Termination requirements are quite different for IO standards, also the chances to achieve reliable signal quality in single ended operaton. You should be more specific about the problem.
 

oh, what i would like to know is why the need for termination to a reference voltage
 

As said, some I/O standards are designed as voltage referenced. But it's not clear if this is the case with your chip. Please give some details for a specific answer.
 

what standard?

there are two issues:
1.) biasing.
2.) inegrity.

ECL/PECL/NECL/LVPECL/*ECL is an example of where both are valued.

ECL can't pull down -- biasing does that.
ECL can't pull up quickly -- biasing helps.

in other cases, termination means that, at very high rates, the singal energies must be reducred and a specific voltage is selected to do this.

more info will give a better response.
 

the datasheet of the chip says to terminate the output via a 50ohm to Vcc - 2V, im not sure of this purpose, cant i just connect the output to another component
 

Sounds like PECL. External termination is required for DC bias of the open-emitter output stage in this case. Unused outputs can be left unconnected. There are of course equivalent termination options to a Vtt voltage source.

You should carefully check, if you get clear logic levels in single ended operation of the PECL outputs, because the voltage swing is low and the common mode voltage varying with temperature. You should better follow the suggestion for PECL level conversion given by the manufacturers.

As a side remark. Mentioning PECL output standard had resulted in a more specific answer a week ago.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top