Problem on Pspice simulation for an inverter ( newbie here)

Hi everyone,

I have a few question for my pspice simulation for an inverter. My Mosfet Vds is very high and how should I do enable to lower the Vds?
How to check the power loss for the Mosfet?
Can you help me check whether the circuit got any problem.
Thanks a lot for you guys help. Really appreciate it.

Hello,

Search for how to drive high side mosfets. An N-channel mosfet requries a gate voltage that is higher then the source voltage.

So when you want the upper mosfets (high side mosfets) to act as a switch, they need a gate voltage that is about 8V above the 50V supply (that is 58V). You need a high side driver for that. Maybe you have some half or full bridge (H-bridge) drivers in your library. As your opamp drivers use +15V, you can't drive the gate of the upper mosfets above 15V.

half or full bridge drivers use a "charge pump" to generate a voltage that is about 10V above the positive supply to feed the actual driver circuitry that drives the high side (upper) mosfets.

Note that mosfet have high resistance for DC, but have capacitance that must be charge and discharged rapidly. Depending on the desired voltage rate of change, this may result in gate peak current in the Ampere range.

Assuming that you don't intend to drive a real H bridge with 741 OPs, you can make your life easy and use simple controlled voltage sources as gate drivers for the simulation.

If your circuit is meaned as a simulation of a real H bridge hardware, reasonable gate drivers for low and high side are urgently required.

power loss for MOSFET = Rds *Ids*Ids and it shouldn't be more than PD(for IRF540 is 130W).

power loss for MOSFET = Rds *Ids*Ids

Click to expand...

This are only on-state losses. Switching losses may be even higher, e.g. with a sloppy gate driver as shown in the original circuit. It can be easily measured in transient simulation Pv=avg(Id*Uds)

Thanks for you guys help. I have simulated the results. as shown in below

However, there is a spike at there, how do I eliminate it? I thought I have already put a snubber circuit parallel to the Mosfet.
and, for the result, How can I get the power loss from the graph? Or is there any library in pspice can help me to calculate power loss?

Thanks a lot again for you guys help, really very appreciate it.

Did you redesign your circuit based on the tips from this thread? If so, please post the new circuit with info where you did measure the waveforms.

Getting impression of loss: plot drain current and drain voltage, multiply the graphs to get instantaneous power. From this instantaneous power curve you can see whether switching loss or conductino loss dominates. The surface below the curve is of importance, not the absolute peak. You may know: P = (1/T)*integral(V*I*dt) over T. You can do the multiplication in the circuit itself as your pspice has a mulitplier block.

If your peak is a current peak, you may increase dead time (that is the time that all mosfets should not conduct). This dead time is required to avoid that a high side mosfet and its corresponding low side mosfet does conduct simultaneously (makes a short duration short circuit). It is also called cross-conduction.

This is my circuit diagram.
Can Pspice help me to plot a graph for drain current vs drain voltage?
How to increase a dead time?

Thanks for yr help. I am new to this field.

Hello,

For getting instantaneous power, you should plot drain voltage and drain current both versus time, and then multiply them. You don't need current versus voltage or vice versa.

Is this circuit just to play with how a H-bridge operates, or are you actaully going to build this circuit (see also FvM's posting). In case of second option, I would recommend you to dive into some existing H-bridge circuits.

You can make dead time by adding some RC section in your circuit. By bridging the R with a diode or diode resistor series circuit, you can get a delay with different delay time for rising and falling edges.

I can't find a gate driver in Pspice. What is the library for gate driver?

I had seen a post regarding to the power loss https://www.edaboard.com/threads/58898/ but as I am using SPWM, the tof and ton will not be the same for every pulse, so, What should I do?

Thanks =)

Hello,

Dead time is the time between the off transition of a low side mosfet and the on transition of the high side mosfet, and vice versa. You can have varying Ton and Toff to generate PWM, but the dead time is to make sure that you have break before make behavior in you H bridge.

If you have make before brake, supply current will shoot through both mosfets resulting in high current peaks, heat, EMC problems, device destruction, etc.

I don't know what is in your library, but with controlled voltage sources, switches, limiters, etc, you can easily make your own driver if this circuit is to learn basics of power electroncis. Multipliers, switches, VCVS, etc are not real components, but just mathematical function blocks in spice that enables you to create lot of functions.

It will make your simulation faster and you have full control over everything, without the limitations in opamps. Other thing, to have some control over dV/dt and dI/dt, actual circuits contain gate resistors frequently (to reduce EMC problems).

If you want to simulate something that you may build, try to locate a full or half bridge driver, or high side driver. Maybe you can use the search function in your library.