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settling issues in post layout simulations of pipelined ADC

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mmkumar

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Hi,

We have designed 14 bit pipelined ADC, which is working up to 120MSPS at schematic level. But, after post layout, I see a settling gets delayed in MDAC (gain of 4) output. I see the dip before raising or very under damped behaviour. I found OTA layout causing more than 1.5 pf extra parasitic capacitance in layout.
 

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