rambleach
Junior Member level 1
Code:
library ieee;
use ieee.std_logic_1164.all;
entity updowncounter is
generic (n: natural := 8);
port ( IC,CLK,upcount,downcount :in std_logic ;
Q: out std_logic_vector(n-1 downto 0) );
end updowncounter ;
architecture exm1 of updowncounter is
begin
prc:process (IC,CLK) is
variable cnt : unsigned (n-1 downto 0); -- the unsigned variable ca take + operation unlike standard logic vector;;;
begin
if IC= '1' then cnt:= (others=> '0');
elsif rising_edge (CLK ) and upcount = '1' then cnt:= cnt + 1;
elsif rising_edge (CLK) and downcount='1' then cnt:= cnt - 1 ;
end if ;
end process prc;
end exm1;error:** Error: C:/Modeltech_pe_edu_10.1a/examples/updowncounter.vhd(13): (vcom-1136) Unknown identifier "unsigned".
** Error: C:/Modeltech_pe_edu_10.1a/examples/updowncounter.vhd(15): Target type (error) in variable assignment is different from expression type.
** Error: C:/Modeltech_pe_edu_10.1a/examples/updowncounter.vhd(15): (vcom-1076) OTHERS choice cannot be used in unconstrained array aggregate.
** Error: C:/Modeltech_pe_edu_10.1a/examples/updowncounter.vhd(16): No feasible entries for infix operator "+".
** Error: C:/Modeltech_pe_edu_10.1a/examples/updowncounter.vhd(16): Bad right hand side (infix expression) in variable assignment.
** Error: C:/Modeltech_pe_edu_10.1a/examples/updowncounter.vhd(17): No feasible entries for infix operator "-".
** Error: C:/Modeltech_pe_edu_10.1a/examples/updowncounter.vhd(17): Bad right hand side (infix expression) in variable assignment.
** Error: C:/Modeltech_pe_edu_10.1a/examples/updowncounter.vhd(20): VHDL Compiler exiting
